Conventionally, a semiconductor chip including a super junction MOSFET and a semiconductor chip including an insulated gate bipolar transistor have been connected in parallel, as shown in Patent Document 1, for example. The term “super junction” is abbreviated hereinafter as SJ. The term “insulated gate bipolar transistor” is abbreviated hereinafter as IGBT. Furthermore, conventionally, an SJ-MOSFET structure is known that includes a p+ collector layer, as shown in Patent Document 2, for example.    Patent Document 1: Japanese Patent Application Publication No. 2014-130909 (US Patent Application Publication No. 2014/184303)    Patent Document 2: Japanese Patent Application Publication No. 2013-102111 (US Patent Application Publication No. 2013/134478)
However, in Patent Document 1, the semiconductor chip including the SJ-MOSFET and the semiconductor chip including the IGBT are connected by wiring to form a module. Therefore, compared to a case where the SJ-MOSFET and IGBT are formed in a single semiconductor chip, the module cannot be miniaturized. In Patent Document 2, the upper border of the depletion layer weakening region including protons is provided in a manner to approximately match the bottom surface of the p-type column layer (see FIG. 1 and paragraphs 0055 and 0056). As a result, the protons that have become donors and the (n−)-type base layer contact each other, and therefore there are more electrons that are carriers in the (n−)-type base layer than holes that are carriers in the p-type column layer, which damages the carrier balance. Accordingly, the depletion layer is difficult to form because of the (n−)-type base layer and the p-type column layer.